تخمین و بهبود آنلاین آسیب پذیری خطای نرم حافظه نهان
محورهای موضوعی : تخصصیمحمد معینی جهرمی 1 , محمد حسن احمدی لیوانی 2 , مصطفی ارسالی صالحی نسب 3 *
1 - دانشکده مهندسي برق و کامپیوتر، دانشکدگان فنی، دانشگاه تهران، تهران، ایران
2 - دانشکده مهندسي برق و کامپیوتر، دانشکدگان فنی، دانشگاه تهران، تهران، ایران
3 - دانشکده مهندسي برق و کامپیوتر، دانشکدگان فنی، دانشگاه تهران، تهران، ایران
کلید واژه: قابلیت اطمینان, خطای نرم, پوشش خطاها, حافظه نهان, آسیبپذیری حافظه نهان, مصالحه قابلیت اطمینان و کارآیی, حجم حافظه نهان, تخمین آسیبپذیری در زمان اجرا.,
چکیده مقاله :
حافظه‌ها به دلیل چگالی بالای ترانزیستورها در آنها به شدت در معرض خطاهای نرم قرار دارند. حافظه نهان پردازنده به دلیل نگه داشتن اطلاعات اجرایی و تعاملات زیاد با آن، قابلیت اطمینان سیستم را به شدت تحت تأثیر قرار میدهد. در سیستم‌های نهفته و کاربردهای ایمنی-بحرانی، اهمیت آن به مراتب بیشتر میشود. از مهم‌ترین پارامترهای تأثیرگذار بر قابلیت اطمینان حافظه نهان، حجم آن است. حافظه نهان با حجم کم‌تر، به واسطه مساحت کوچک‌تر و ماندگاری کم‌تر داده‌ها در آن قابلیت اطمینان بیشتری دارد اما، کاهش حجم حافظه نهان، مدت اجرای برنامهها را طولانیتر می‌کند. این افزایش زمان اجرای برنامهها، احتمال بروز خطای نرم را افزایش میدهد. از سویی، قابلیت اطمینان حافظه نهان در طول اجرای یک برنامه یکنواخت نیست و ثابت بودن حجم حافظه نمی‌تواند قابلیت اطمینان آن را در طول اجرا بهینه کند. در این راستا، مسأله اصلی در بهبود آسیبپذیری حافظه نهان، تعیین اندازه حافظه نهان و زمان تغییر آن با توجه به سربار تغییرات است. بر همین مبنا، در این مقاله مدلی برای تخمین آسیبپذیری حافظه نهان تعریف شده است که بر اساس دادههای حافظه نهان و نوع دسترسی به آنها، آسیبپذیری آن تعیین میشود. بر اساس مدل ارائه شده، الگوریتمی پیادهسازی شده است که آسیبپذیری حافظه نهان را در زمان اجرا به صورت آنلاین تخمین میزند. برای مدلسازی زمان در این روش، از شمارندههایی استفاده شده است که در طول بازههای تصمیمگیری، زمان دسترسیها را مدل میکنند. با استفاده از تخمین بلوک بجای کلمات حافظه و تعیین اندازه شمارندهها و بازههای تصمیمگیری، روش ارائه شده، بهینهسازی شده است. دقت تخمین روند آسیبپذیری نسبت به مدل رفرنس، 22/95% میباشد. همچنین با استفاده از تخمین روند آسیبپذیری در زمان اجرا و اندازه موثر حافظه نهان هر برنامه، الگوریتمی جهت بازپیکربندی حافظه نهان در جهت بهبود آسیبپذیری آن ارائه شده است. پیادهسازی این طراحی نشان داده است که تنها با سربار مساحت %4/5 و سربار زمانی %6 می‌توان یک حافظه با قابلیت بازپیکربندی و مجهز به الگوریتم مدیریت آسیبپذیری داشت که آسیبپذیری آن در زمان اجرا از آسیبپذیری حافظه نهان با حجم ثابت کم‌تر و آسیبپذیری کل آن نیز %36 بهتر باشد.
Due to the high density of transistors, memories are highly susceptible to soft errors. The processor's cache, by holding execution data and having frequent interactions with it, greatly impacts system reliability. This importance is even higher in embedded systems and safety-critical applications. One of the most significant factors affecting the reliability of the cache is its size. Smaller caches have better reliability due to their smaller area and shorter data retention, but reducing the cache size makes program execution times longer. This increases the probability of a soft error. Furthermore, reliability of cache is not uniform during program execution, and fixed size of memory cannot optimize its reliability during this time. In this regard, the main issue in improving cache vulnerability is to determine an optimum size of cache and its change time according to change overhead. Accordingly, this paper defines a model for estimating cache vulnerability, which determines vulnerability based on cache data and the type of access to it. Based on the proposed model, an algorithm has been implemented that estimates cache vulnerability online during execution. To model time in this approach, counters are used that model access times during decision-making intervals. By estimating based on blocks instead of memory words and determining the sizes of the counters and decision intervals, the proposed method has been optimized. The accuracy of the vulnerability trend estimation compared to the reference model is 95.22%. Additionally, by using the estimated vulnerability trend during execution and the effective cache size of each program, an algorithm for reconfiguring the cache to improve its vulnerability has been proposed. Implementation showed that with only 5.4% area overhead and 6% time overhead, we can have a reconfigurable memory equipped with a vulnerability management algorithm, which has a lower runtime vulnerability than a fixed cache size and overall vulnerability improvement of 36%.
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