Design of FPGA-based processor for SHA-2 series cryptographic algorithms Design ترجمه‌های design اسمفراوانی طرح plan, design, layout, project, scheme, plot نقشه map, plan, plot, scheme, plat, chart زمینه background, context, ground, setting, base, terrain تدبیر measure, plan, contraption, gimmick, contrivance, scheme قصد intention, intent, purpose, attempt, will, determination طراح ریزی design خیال imagination, phantom, illusion, thought, fiction, mind فعل طرح کردن design, plan, draft, draw, lay, bring forth قصد کردن attempt, decide, design, meditate تخصیص دادن allot, allocate, apportion, consecrate, give, design تدبیر کردن devise, contrive, meditate, compass, machinate, design تعریف‌های design اسم ۱ a plan or drawing produced to show the look and function or workings of a building, garment, or other object before it is built or made. he has just unveiled his design for the new museum مترادف‌ها: planblueprintdrawingscale drawingsketchoutlinemapplotdiagramdelineationdraftdepictionrepresentationartist's impressionschememodelprototypeproposal ۲ an arrangement of lines or shapes created to form a pattern or decoration. pottery with a lovely blue and white design مترادف‌ها: patternmotifdevicestylearrangementcompositionmakeuplayoutconstitutionconfigurationorganizationconstructionshapeformformationfigure purpose, planning, or intention that exists or is thought to exist behind an action, fact, or material object. the appearance of design in the universe مترادف‌ها: intentionaimpurposeplanintentobjectiveobjectgoalendtargetpointhopedesirewishdreamaspirationambitionidea فعل ۱ decide upon the look and functioning of (a building, garment, or other object), by making a detailed drawing of it. a number of architectural students were designing a factory مترادف‌ها: plandraw plans ofdrawsketchoutlinemap outplotblock outdelineatedraftdepictinventoriginatecreatethink upcome up withdeviseformformulateconceivemakeproducedevelopfashionfabricateforgehatchcoindream up مترادف design اسم planpatternintention فعل planinventdream upintend ۹۱ مترادف دیگر
Subject Areas : General
neda sedghahrabi
1
,
Mohammad Ali Jabraeil Jamali
2
*
1 -
2 -
Keywords: Secure decoder algorithms, SHA-2 series encryption algorithms, CPU, VHDL, FPGA,
Abstract :
Secure decryption algorithms are a type of cryptographic algorithms whose importance in today's society has been highlighted by applications such as the use of personal digital tools to maintain confidentiality. On the other hand, with the advancement of technology, the need to implement these algorithms on flexible platforms can be challenging. Reducing the area and speeding up the execution of operations are the main challenges for designing and implementing these algorithms. This paper proposes a new architecture for the FPGA-based processor for SHA-2 series cryptographic algorithms. In the proposed processor, the use of memory units and multi-port data path, followed by parallel processor performance, has reduced the use of resources and increased the speed of data processing. Processor architecture for SHA-2 cryptographic algorithms is modeled in VHDL and implemented on the FPGA platform in the Virtex series by ISE software. Implementation results show that the proposed compact processor compared to previous tasks with similar objectives, was able to increase the operating frequency for the SHA-256 cryptographic algorithm by 25% and occupy 55% less space for the SHA-512 cryptographic algorithm to the desired level of operational power and efficiency. Also maintain. The proposed processor is suitable for applications such as trusted mobile platforms (TMP), digital currency (Bitcoin) and secure on-chip network routing (NoC).
1. ذاکر حسینی ، ملکیان،. امنیت داده‌ها، ویراسته 1. باباخانی، ویرایش دوم، تهران، موسسه علمی-فرهنگی نص، 1387.
2.E. Kurniawan & I. Riadi, “Security Level analysis Of academic information systems based on standard ISO 27002:2003 using SSE-CMM’’,vol. 16,no. 1, pp. 139-147,2018.
3.I. Riadi, E. I. Aristianto & A. Dahlan, “An Analysis of Vulnerability Web Against Attack Unrestricted Image File Upload’’, Comput. Eng. Appl., vol. 5, no.1, PP. 19-28,2016.
4.H. Kim, M. Lee, D. K. Kim, S. K. Chung&K. Chung, “Design and implementation of crypto co-processor and its application to security systems”, BerlinHeidelberg: Springer, Computational Intelligence and Security. Lecture Notes in Computer Science, vol. 3802, PP. 1104–9, 2005.
5.S. Reddy, R. Sakthivel&P. Praneet, “VLSI implementation of AES crypto processor for high throughput,” In: (IJAEST) International Journal of Advanced Engineering Sciences and Technologies, vol. 6, PP. 2–6, 2011.
6. دری، قیاسیان، سعیدی،. «طراحی و پیاده‌سازی رمزنگار AES در بستر FPGA برای خطوط پرسرعت»، مجله مهندسی برق دانشگاه تبریز، جلد 46، شماره 1، بهار 1395.
7.R. Glabb, L. Imbert, G. Jullien, A. Tisserand and N. Veyrat-Charvillon, “ Multi-mode operator for SHA-2 hash functions”,JSystArchit 53(2-3):127-38, 2007.
8.N. Sklavos& O. Koufopavlou, “On the hardware implementations of the SHA-2 (256,384,512) hash functions”, In Proceeding of the 2003 International Symposium on Circuits and Systems, ISCAS’03.vol.5;2003.p.V-153-V-156, 2003.
9.K. Ting, S. Yuen,K.Lee and P. Leong, “An FPGA based SHA -256 processor”, In: Glesner M, Zipf P, Renovell M, editors. Field-Programmable Logic and Applications: Reconfigurable Computing is Going Mainstream, Lecture notes in Computer Science, vol. 2438. Berlin/Heidelberg: Springer, p. 449–71, 2002.
10.http:// www.en.wikipedia.org/wiki/securehashalgorithm.
11.U.S. Department of Commerce National Technical Information Service,FIPS180-2–Secure Hash Standard,http://www.csrc.nist.gov/publications/fips/fips180-2/fips180-2, 2002.
12.N. Sklavosand & O.KouFOPAVLOU, “Implementation of the SHA-2 hash family standard using FPGAs”, Springer Science+Business Media, Inc. Manufactured in the Netherlands, The Journal of supercomputing, vol. 31, pp. 227-248, 2005.
13.A. Regenscheid, R. Perlner, S. Chang, J. Kelsey,M. NandiandandS. Paul, Status Report on the First Round of the SHA-3 Cryptographic Hash Complete Competition, NIST, 2009.
14.E. Andreeva,B. Menninkand and B. Preneel, “Security reductions of the second round SHA_3 candidates,” In: Proceedings of the 13thInternational Conference on Information Security, ISC’10. Berlin, Heidelberg: Springer-Verlag, PP. 39–53, 2011.
15.P. Kotewar, R. Mandavganeand & D. Khatri, “Review on area optimization and simulation of SHA-3,”Journal of Emerging Technologies and Innovative Research (JETIR), PP.290-292, 2014.
16.F. Crowe, A. Daly, T. Kerins and W.Marnane, “Single-chip FPGA implementation of acryptographic co-processor”, In: Proceedings: IEEE International Conference on Field-Programmable Technology(IEEE Cat. No.04EX921), PP. 279–285,2005.
17.R. Lien, T. Grembowski and K. Gaj,A1Gbit/s Partially Unrolled Architecture of Hash Function SHA-1 & SHA-512, In: Topics in Cryptography a CT-RSA, pp.1995-1999, 2004.
18.A.P. Kakarountas,H. Michail,A. Milidonis, C.E. Goutis &G. Theodoridis, “High-speed FPGA implementation of secure hash algorithm for IPSec and VPN applications”, Journal of Supercomputing, vol. 37, PP.179-195, 2006.
19.Y. Yang, F. Chen, Z. Sun, S. Wang, J. Li, J. Chen &Z. Ming, “Secure and efficient parallel hash function construction and its application on cloud audit”, Soft Computing, vol. 23, pp. 8907-8925, 2019.
20.Y. K. Lee, H. Chan and I. Verbauwhede,“Iteration bound analysis and throughput optimum architecture of SHA-256(384,512) for hardware implementations”, In:Proceedings of the 8th International Conference on Information Security Applications, vol 256, PP.102–114, 2007.
21.M. Kim,J. Ryouand &S. Jun, “Efficient hardware architecture of SHA-256 algorithm for trusted mobile computing,” Information Security &Cryptology, Lecture Notes in Computer Science, Berlin Heidelberg: Springer, vol.5487, p. 240–52, 2009.
22.R. Chaves, G. Kuzmanor, L. Sousaand & S. Vassiliadis, “Cost efficient SHA hardware accelerators”, IEEE Transaction on Very Large Scale Integration Systems, Vol.16,NO.8, PP.999-1008, 2008.
23.G. Feng, P. Jainand & K. Choi, “Ultra-low power and high speed design and implementation of AES and SHA1 hardware cores in 65 nanometer CMOS technology”, In Electro/Information Technology,IEEE International Conference, PP.405-410, 2009.
24.M. Sumagita&I. Riadi, “Analysis of Secure Hash Algorithm (SHA) 512 for Encryption Process on Web Based Application”, IJCSIS Int. J. Dig. Foren. Cyb. Secur., vol. 7, no. 4, pp. 373-381, 2018.
25.M.I.Mazdadi, I. Riadi&A. Luthfi, “Live Forensics on RouterOS API Services to Investigate Network Attacks”, Int. J. Comput. Sci. Inf. Secur., Vol. 15, no. 2, pp.406-410, 2017.
26.W. Stallings, Cryptography and Network Security Principles and Practice, Fifth Edition, Pearson Education, Inc., Publishing as Prentice Hall, 2011.
27.A.L. Barkatullah& T. GailaniCelebi, Design and FPGA Implementation of Hash Processor, Master of Science thesis, Middle East Technical University, 2007.
28.R. Garcia, I. Algredo-Badillo, M.,Morales-Sandoval, C.Feregrino-Uribeand and R. Cumplido, “A compact FPGA-based processor for the secure hash algorithm SHA-256”,Elsevier, Computers and Electrical Engineering, vol. 40, pp. 194-202, 2014.
29.H. E. Michail, G.S.Athanasiou,G. Theodoridisand & C. E. Goutis, “On the development of high-throuput and area-efficient multi-mode cryptographic hash designs in FPGA”, Elsevier,Integration,The VLSI Journal, vol. 47, pp.387-407, 2014.
30.X. Cao,L.Luand & M. O’Neill, “A compact SHA-256 architecture for RFID tag,”,In: Proceedings of the 22nd IET irishSignals and Systems Conference, ISSC, Trinity CollegeDublin, 2011.
31.M. Kim, D. Lee and J. Ryou, “Compact and Unified Hardware Architecture for SHA-1 and SHA-256 of Trusted Mobile Computing”, PersUbiquitComput 2012:1–12,http://www.dx.doi.org/10.1007/s00779-012-0543.
32.C. Jeong& Y. Kim, “Implementation of efficient SHA-256 hash algorithm forsecure vehicle communication using FPGA”, IEEE, ISOCC2014, PP. 224-226,2014.
33.H. Michail,“On the exploitation of a high-throughput SHA-256 FPGA design for HMAC, ”ACM Trans on Reconfigurable Tech. and Sys.,vol. 5 no. 1,pp. 1- 28, 2012.
34.M.Zeghid, B. Bouallegue, A. Baganne, M. Machhoutand &R. Tourki,“A reconfigurable implementation of the new secure hash algorithm”,Proc Second Int. Conf. Availability, Reliability and Security, (ARES2007), 10–13 April 2007.
35.P. Zawleski, M. Lukowiakand &S. Radziszowsk, Case Study on FPGA Performance of Parallel Hash Function,PrzegladElectrotechniczny/ElectricalReview, PP. 151-155,2010.
36.H. Technology, Efficient Tiny Hash Core Family for Xilinx FPGA Datasheet, Helion Technology Limited, 2010.
37.I. Algredo-Badillo,M. Morales-Sandoval, C. Feregrino-Uribe and R. Cumplido,“Throughput and efficiency analysis of unrolled hardware architectures for the SHA-512 hash algorithm”,IEEE Computer Society Annual Symposium on VLSI, PP. 63- 68, 2012.
38.G. Athanasiou, H. Michail, G. Theodoridis and C. Goutis,“Optimising the SHA-512 cryptographic hash function on FPGAs”, Published in IET Computers & DigitalTechniques, PP.70-83,2013.