Adaptive rotation models and traffic patterns to reduce light loss in networks on optical chip
Subject Areas : General
bahareh asadi
1
()
midia reshadi
2
()
Ahmad khademzade
3
()
mostafa karbasi
4
()
Keywords: Light dissipation, traffic patterns, rotational models, router,
Abstract :
Large number of processing cores integrated into a single chip have high growth rates. Networks on an optical chip are one of the simplest ways to solve the addressing problem between bulk interconnected networks. That's why high-performance, high-bandwidth multi-processor chips will be needed in the future. Optical chip networks were introduced as a new generation of on-chip networks that overcome all the limitations of this type of network and have many advantages such as high communication bandwidth, low transmission delay. And power consumption is low. On the other hand, networks on optical chips have challenges, one of the most important of which is the routing of optical data in the optical layer, because how the path is selected affects the optical loss factor. In this paper, routing algorithms free from the impasse of adaptive rotational models, circuit switching and various traffic patterns to reduce light loss in the optical layer by considering a 5-port unobstructed router and two-dimensional grid or Mesh will be provided. Finally, we compare the simulation results with similar methods such as the XY-based algorithm and examine the improvements obtained.
1.Shacham A, Bergmen K, Carloni LP (2008) Photonic Network-on-Chip for Future Generations of Chip Multiprocessors. IEEE Trans Comput 57: 1246-1260. doi: 10.1109/TC.2008.78
2.Hung MK, Yaoyao Y, Xiaowen W, Wei Z, Weichen L, Jiang X (2010) A Hierarchical Hybrid Optical-Electronic Network-on-Chip. In Proc IEEE Compute SOC Ann Symp 327-332. doi: 10.1109/ISVLSI.2010.17
3.Miller DAB (2009) Device Requirements for Optical Interconnects to Silicon Chips. Proc. IEEE 977:1166-1185. doi: 10.1109/JPROC.2009.2014298
4.Lee BG, Biberman A, Chan J, Bergmen K (2010) High-Performance Modulators and Switches for Silicon Photonic-Network-on-Chip. IEEE J. Sel. Topics Quantum Electron 16: 6-22. doi: 10.1109/JSTQE.2009.2028437
5.Min R, Ji R, Chen Q, Zhang L (2012) A Universal Method for Constructing N-Port Nonblocking Optical Router for Photonic Networks-on-Chip. Journal of Lightwave Technology 30: 3736-3741. doi: 10.1109/JLT.2012.2227945
6.Beausoleil RG, Kuekes PJ, Snider GS, Yuan WS, Williams RS (2008) Nanoelectronic and Nanophotonic Interconnect. Proceeding of the IEEE 96: 230-247. doi: 10.1109/JPROC.2007.911057
7.Xie Y, Nikdast M, Xu J, Wu X, Zhang W, Ye Y, Wang X, Wang Z, Liu W (2012) Formal Worst-Case Analysis of Crosstalk Noise in Mesh-Based Optical Networks-on-Chip. IEEE Transaction on very large Scale integration (VLSI) Systems 21:1823-1836. doi: 10.1109/TVLSI.2012.2220573
8.Chan J, Hendry G, Bergman K, Carloni LP (2011) Physical-Layer Modeling and System-Level Design of Chip-scale Photonic Interconnection Networks. Computer-Aided Design of Integrated Circuits and Systems, IEEE Trans, 30: 337-345. doi: 10.1109/TCAD.2011.2157157
9.Biberman A, Preston K, Hendry G, Sherwood N, Chan J, Levy JS, Lipson M, Bergman K (2011) Photonic Network-on-Chip Architectures Using Multilayer Deposited Silicon Materials for High-Performance Chip Multiprocessor. J. Emerge Techno Compute Syst 7:1-25. doi: 10.1145/1970406.1970409
10.Pan Y, Kumar P, Kim J, Memik G, Zhang Y, Choudhary A (2009) Firefly: Illuminating Future Network-on-Chip with Nanophotonics. Presented at the Proceedings of the 36th Annual International Symposium on Computer Architecture Austin Texas USA 429-440.
11.Hatamirad M, Reza A, Shabani H, Niazmand B, Reshadi M (2012) Loss-Aware Router Design Approach for Dimension-ordered Routing Algorithms in Photonic Networks-on-Chip. IJCSI International Journal of Computer Science Issues 9: 337-345.
12.Xie Y, Nikdast M, Xu J, Zhang W, Li Q, Wu X, Ye Y, Wang X, Liu W (2010) Crosstalk Noise and Bit Error Rate Analysis for Optical Network-on-Chip. DAC’10 Anaheim California USA 657-660.
13.Shacham A, Hendry G, Bergman K, Carloni LP (2007) On the Design of a Photonic Network-on-Chip. In networks-on-chip first International Symposium 53-64.
14.Gu H, Hung KM, Xu J, Zhang W (2009) A Low-power Low-cost Optical Router for Optical Networks-on-Chip in Multiprocessor System-on-Chip. IEEE Computer Society Annual Symposium on VLSI 19-24. doi: 10.1109/ISVLSI.2009.19
15.Ye Y, Wu X, Xu J, Zhang W, Nikdast M, Wang X (2012) Holistic Comparison of Optical Routers for Chip Multiprocessors. Supported by RPC11EG18 and SBI06/07. EG01-4 1-5. doi: 10.1109/ICASID.2012.6325348
16.Gu H, Xu J, Wang Z (2008) A Novel Optical Mesh Network-on-Chip for Gigascale Systems-on-chip. IEEE 1728-1731. doi: 10.1109/APCCAS.2008.4746373
17.Ji R, Yang L, Zhang L, Tian Y, Ding J, Chen H, Lu Y, Zhou P, Zhu W (2011) Five-port Optical Router for Photonic Networks-on-Chip. Optics Express, 19: 20258-202668. doi: 10.1364/OE. 19.020258
18.Shacham A, Lee BG, Chen Q, Carloni LP (2007) Photonic NoC for DMA Communications in Chip Multiprocessors. 15th IEEE Symposium on High-performance Interconnects IEEE Computer Society 29-38. doi: 10.1109/HOTI.2007.9
19.Vantrease D (2008) CORONA: System Implications of Emerging Nanophotonic Technology. In Computer Architecture, ISCA ’08. 35th International Symposium, 153-164. doi: 10.1109/ISCA.2008.35
20.Joshi A (2009) Silicon-Photonic CLOS Networks for Global on-Chips Communication. In Networks-on-Chip 3RD ACM/IEEE International Symposium, 124-133. doi: 10.1109/NOCS.2009.5071460
21.Koohi S, Abdollahi M, Hessabi S (2011) All-Optical Wavelength-Routed NoC based on a Novel Hierarchical Topology. In Networks-on-Chips (NoCs) Fifth IEEE/ACM International Symposium 97-104.
22.Sherwood-Droz N, Wang H, Chen L, Lee BG, Biberman A, Bergman K, Lipson M (2008) Optical 4*4 Hitless Silicon Router for Optical Networks-on-Chip (NoCs). Opt. Express 16:15915-15922. doi: 10.1364/OE. 16.015915
23.G (2011) Time-Division-Multiplexed Arbitration in Silicon Nanophotonic Networks-on-Chip for High Performance Chip Multiprocessors. J. Parallel Distrib Compute 71: 641-650. doi:10.1016/j.jpdc.2010.09.009
24.Wu Chan J (2012) Architecture Exploration and Design Methodologies of Photonic Interconnection Networks. Columbia University, Columbia, New York City.
25.Mo KH, Ye Y, Wu X, Zhang W, Liu W, Xu J (2010) A Hierarchical Hybrid Optical-Electronic Network-on-Chip. Presented at the proceedings of the 2010 IEEE Annual Symposium on VLSI.
26.Nikdast M, Xu J (2007) Crosstalk noise and Loss Analysis Platform (CLAP) publishing Hong Kong University of Science and Technology. http://www.ece.ust.hk/~eexu/CLAP.html.
27.Chan J, Hendry G, Biberman A, Bergman K, Carloni LP (2010) Phoenixsim: A simulator for physical-layer analysis of chip-scale photonic interconnection networks. Proceedings of the Conference on Design Automation and Test in Europe 691-696.
28.Singh A (2005) Load-balanced routing in interconnection networks. Submitted to the department of electrical engineering and the committee on graduate studies of Standford University in partial fulfillment of the requirements for the degree of Doctor of Philosophy.
29.Hendry G, Kamil S, Biberman A, Chan J, Lee B. G, Mohiyuddin M, Bergman K, Carloni L. P, Oliker L, Shalf J (2009) Analysis of Photonic Networks for a Chip Multiprocessor Using Scientific Applications. 3rd ACM/IEEE International Symposium 104-113. doi: 10.1109/NOCS.2009.5071458.
30.Hendry G (2011) Architectures and Design Automation for Photonic Networks on Chip. Submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy in the Graduate School of Arts and Sciences Columbia University.