طراحی روتر نوری غیربلاک هفت پورت و ارائه الگوریتم مسیریابی موثر در شبکه بر تراشه نوری سه بعدی
محورهای موضوعی : فناوری اطلاعات و ارتباطاتساناز اسدي نيا 1 * , الهام یعقوبی 2 , مصطفی صادقی 3
1 - دانشکده مهندسی کامپیوتر، واحد اصفهان، دانشگاه آزاد اصفهان، اصفهان، ایران
2 - دانشکده مهندسی کامپیوتر، واحد نجف آباد، دانشگاه آزاد نجف آباد، اصفهان، ایران
3 - دانشکده مهندسی کامپیوتر، واحد اصفهان، دانشگاه آزاد اصفهان، اصفهان، ایران
کلید واژه: شبکه بر تراشه نوری سه بعدی, مسیریاب نوری, میکرورینگ رزوناتور, اتلاف, توان مصرفی,
چکیده مقاله :
شبکه بر تراشههای سه بعدی در سالهای اخیر، بعنوان یک راه حل بهینه برای غلبه بر محدودیت پهنای باند اتصالات الکتریکی در پردازنده های چندهستهای مورد توجه محققان قرار گرفته است. استفاده از تکنولوژی ارتباطات نوری در این شبکه ها، در معماریهای چند هسته ای افزایش کارایی را بهمراه داشته است. در ساختار شبکه های نوری روی تراشه سه بعدی از روترهای ۴و۵ پورت در گوشههای شبکه نوری و برای انتقال داده ها در این نوع شبکه از روترهای ۶ و ۷ پورت استفاده میشود. در این مقاله، روتر نوری غیرانسدادی ۷ پورت مبتنی بر ریزحلقه تشدیدگر ارائه شده است. روتر پیشنهادی توانسته است با کاهش تعداد عناصر سوییچینگ نوری، توان مصرفی و اتلاف انرژی را به طور قابل ملاحظه ای کاهش دهد. همچنین در این مقاله یک الگوریتم مسیریابی جدید با هدف یافتن بهترین مسیر با در نظر گرفتن کاهش اتلاف انرژی و توان مصرفی برای شبکه بر تراشههای نوری سه بعدی پیشنهاد شده است. این الگوریتم بر روی روتر پیشنهادی اجرا شده است که میتواند بهترین مسیر میان هستههای پردازشی مبدا و مقصد را با توجه به معماری روتر نوری پیشنهادی و با استفاده از مدلهای چرخشی به گونه ای انتخاب کند که کمترین اتلاف انرژی و توان مصرفی را نسبت به بقیه مسیرها داشته باشد. ارزیابی پارامترهای اتلاف انرژی و توان مصرفی با استفاده از شبیهسازی که بر روی بستر نرمافزار Omnet++ نصب میشود انجام شده است. نتایج حاصل از شبیه سازی نشاندهندهی بهبود کارایی شبکه بر تراشه نوری سه بعدی نسبت به شبکههای موجود میباشد.
In recent years, three-dimensional Networks-on-Chip (3D NoCs) have been recognized as an effective solution to overcome the bandwidth limitations of electrical interconnects in multi-core processors. The adoption of optical communication technologies in these networks has significantly enhanced the performance of multi-core architectures. In 3D Optical NoC structures, 4-port and 5-port routers are typically deployed at the network corners, while 6-port and 7-port routers are employed for data transmission across the network.
In this paper, we propose a non-blocking 7-port optical router based on microring resonators. The proposed router achieves substantial reductions in power consumption and energy loss by minimizing the number of optical switching elements. Furthermore, a novel routing algorithm is introduced, aiming to determine the optimal data path while reducing energy dissipation and power consumption for 3D Optical NoCs. This algorithm is implemented on the proposed router and dynamically selects the most efficient path between the source and destination processing cores by leveraging the router’s architecture and rotational models, ensuring minimal energy and power usage compared to other available paths.
The evaluation of energy loss and power consumption parameters has been conducted through simulations on the Omnet++ platform. The obtained results demonstrate that the proposed design significantly improves the performance of 3D Optical NoCs compared to existing architectures.
[1] L. Weichen, T. Guiyu, L. Mengquan, “Autonomous Temperature Sensing for Optical Network-on-Chip”. Journal of Systems Architecture, January 2020, 101650
. [2] HUSEYúIN T, KAYHAN M, “Scheduling Computation and Communication on a Software-Defined Photonic Network-on-Chip Architecture for High-Performance Real-Time Systems”, Journal of Systems Architecture, October 2018, Pages 54-71
. [3] S. Asadinia, M. Mehrabi, E. Yaghoubi, “Surix: Non‑blocking and low insertion loss micro‑ring resonator‑based optical router for photonic network on chip,” The Journal of Supercomputing, https://doi.org/10.1007/s11227-020-03442-4, 2020
. [4] S. Asadinia, E. Yaghoubi, M. Mehrabi, “3D Mesh ONoC: Design of low Insertion Loss and Non-blocking Optical Router and Efficient Routing Algorithm,” 14th International Conference on Information and Knowledge Technology (IKT), 2023, DOI: 10.1109/IKT62039.2023.10433045
. [5] A.W. Poon, F. Xu, and X. Luo, “Cascaded active silicon micro resonator array cross-connect circuits for WDM networkson-chip,” in Proc. SPIE, vol. 6898, pp. 689812-689812-10, 2008
. [6] Y. Ye et al., “3-D mesh-based optical network-on-chip for multiprocessor system-on-chip,” IEEE Trans. Comput. -Aided Des. Integr. Circuits Syst., vol. 32, no. 4, pp. 584–596, Apr. 2013
. [7] Ben Ahmed A, Ben Abdallah A,” Hybrid silicon-photonic network-on-chip for future generations of high-performance many-core systems, “The Journal of Supercomputing, DOI: 10.1007/s11227-015-1539-0
. [8] A. Reza, Sarbazi-Azad H, A. Khademzadeh, H. Shabani, Niazmand B,” A loss aware scalable topology for photonic on chip interconnection networks, “The Journal of Supercomputing, DOI: 10.1007/s11227-013-1026-4
. [9] Pengxing Guo, Weigang Hou, Lei Guo, Wei Sun, Chuang Liu, Hainan Bao, Luan H. K. Duong, and Weichen Liu,” Fault-Tolerant Routing Mechanism in 3D Optical Network-on-Chip based on Node Reuse,” IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS
. [10] J. Hao, Ting Zh, Yunchou Zh, X. Yuhao, D. Jincheng, Lei Zh, D. Jianfeng, Xin F and Lin Y, "Six- port optical switch for cluster-mesh photonic network-on-chip", Nanophotonics; 7(5): 827–835, 2018: 827–835,2018.
[11] A. Shacham, K. Bergman, and L. P. Carloni, “Photonic networks-on-chip for future generations of chip multiprocessors,” IEEE Trans. Comput., vol. 57, no. 9, pp. 1246–1260, Sep. 2008.
[12] Y. Xie, W. Zhao, W. Xu, Y. Huang, and Z. Zhang, “Performance optimization and evaluation for mesh-based optical networks-on-chip,” IEEE Photon. J., vol. 7, no. 4, Aug. 2015, Art. No. 7801412.
[13] J. H. Lau, “Through-Silicon Vias for 3D Integration,” New York, NY, USA: McGraw-Hill, 2012, ISBN-13 978-0071785143.
[14] K. Zhu, H. Gu, Y. Yang, W. Tan, and B. Zhang, “A 3D multilayer optical network on chip based on mesh topology,” Photon. Netw. Commun. vol. 2016, no. 3, pp. 293–299, 2016
. [15] J. H. Lee, “Insertion Loss-Aware Routing Analysis and Optimization for a Fat-Tree-Based Optical Network-on-Chip”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 37. No. 3, pp. 559-572
. [16] P. Guo, W. Hou, L. Guo, Q. Yang, Y. Ge, Liang H ,” Low Insertion Loss and Non-Blocking Microring-Based Optical Router for 3D Optical Network-on-Chip,” IEEE Photonics Journal. DOI:10.1109/JPHOT.2018.2796094
. [17] P. Guo, W. Hou, and L. Guo, “Designs of low insertion loss optical router and reliable routing for 3D optical network on-chip,” Sci. China-Inf. Sci., vol. 59, no. 10, 2016, Art. No. 102302
. [18] W. Hou, L. Guo, Q. Cai, and L. Zhu, “3D Torus ONoC: Topology design, router modeling and adaptive routing algorithm,” in Proc. IEEE Int. Conf. Opt. Commun. Netw, 2014, pp. 1–4
. [19] S. Asadinia, M. Mehrabi, E. Yaghoubi, “Non-Blocking and Multi Wavelength Optical Router Design based on Mach-zehnder Interferometer in 3-D Optical Network on Chip,” Majlesi Journal of Electrical Engineering, 2021, DOI: https://doi.org/10.52547/mjee.15.2.73
. [20] N. Dahir, T. Mak, Al-Dujaily R, Yakovlev A,” Highly adaptive and deadlock-free routing for three-dimensional networks-on-chip. “IET Computers & Digital Techniques. 2013, Vol. 7, No. 6, pp. 255-263
. [21] Chiu G.M,” The odd-even turn model for adaptive routing. IEEE Transactions on Parallel and Distributed Systems, “2000, Vol. 11, No. 7, pp. 729-738
. [22] P. Bahrebar, Stroobandt D,” The Hamiltonian-based odd–even turn model for maximally adaptive routing in 2D mesh networks-on-chip. “Computers & Electrical Engineering, 2015, Vol. 45, No. pp. 386-401
. [23] A. Shacham, K. Bergman, Carloni L.P,” On the Design of a Photonic Network-on-Chip. “First International Symposium on Networks-on-Chip (NOCS'07), 2007, pp. 53-64, 7-9
. [24] Huaxi Gu, Jiang Xu, 2009. "Design of 3D Optical Network on Chip", in Proc. Conf., 2009, IEEE
. [25] Yaoyao Ye, Xiaowen Wu, Mahdi N,” 3-D Mesh-Based Optical Network-on-Chip for Multiprocessor System-on-Chip.” IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2013, VOL. 32, NO. 4
[26] Kexin Zhu, Huaxi GU, Yintang Yang, Wei Tan, Bowen Zhang,” A 3D multilayer optical network on chip based on mesh topology. “Photon Netw Commun. 2016, DOI 10.1007/s11107-016-0627-2
. [27] Muhammad R.Y, Ning Wu, Gaizhen Yan, A. Tanveer, Jinbao Z and Yuanyuan Z,” HoneyComb ROS: A 6 * 6 Non-Blocking Optical Switch with Optimized Reconfiguration for ONoCs. “Electronics 2019, 8, 844; doi:10.3390/electronics8080844
. [28] J. Chan, G. Hendry, A. Biberman, K. Bergman, Carloni L.P,” Phoenixsim: a simulator for hysical-layer analysis of chip-scale photonic interconnection networks.” 2010, Proceedings of theConference on Design Automation and Test in Europe 691–696
. [29] A. Varga, Hornig R,” An overview of the OMNeT++simulation environment. “In: Proceedings of the 1st International Conference on Simulation Tools and Techniques for Communications, Networks and Systems and Workshops, 2008, ICST (Institute for Computer Sciences, Social-Informatics and Telecommunications Engineering), p 60
. [30] Varga A,” The OMNeT++discrete event simulation system. “In: Proceedings of the European Simulation Multi conference (ESM’2001), vol S 185. sn, p 65 The OMNeT++discrete event simulation system
. [31] J. Chan, A. Biberman, Lee B.G, Bergmann K,” Insertion loss analysis in a photonic interconnection network for on-chip and off-chip communications. “21st Annual Meeting of the IEEE Lasers and Electro-Optics Society, 2008, pp. 300-301, 9-13
. [32] R. Ji, L. Yang, L. Zhang, Y. Tian, J. Ding, H. Chen, Y. Lu, P. Zhou, Zhu W,” Microring-resonator-based four-port optical router for photonic networks-on-chip.” Optics Express. Vol. 19, No. 20, pp. 18945-18955
. [33] Chaudhari B. S, Patil S. S,” Optimized designs of low loss non-blocking optical router for ONoC applications.” 2019, (IJIT). DOI: 10.1007/s41870-019-00298-7
. [34] J. Chan, G. Hendry, K. Bergman, Carloni L.P,” Physical-Layer Modeling and System-Level Design of Chip-Scale Photonic Interconnection Networks.” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems. 2011, vol. 30, no. 10, pp. 1507-1520. DOI:10.1109/TCAD.2011.2157157
. [35] Lee B. G, A. Biberman, D. Po, M. Lipson, Bergman K,” All-Optical Comb Switch for Multi wavelength Message Routing in Silicon Photonic Networks.” 2008, IEEE Photonics Technology Letters, vol. 20, no. 10, pp. 767-769
. [36] N Bagheri Renani, E Yaghoubi,” A Review of Optical Routers in Photonic Networks-on-Chip,” A Literature Survey. J. ADV COMP ENG TECHNOL. 2018, 4(3) pp. 143-154
[37] N.B. Renani, E.Yaghoubi, N Sadehnezhad, et al. “NLR-OP: a high-performance optical router based on North-Last turning model for multicore processors.” J Supercomput ,2022, 78, 2442–2476. DOI: 10.1007/s11227-021-03920-3
.